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XR18W750
REV. 1.0.0
WIRELESS UART CONTROLLER
3.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs to their default state (see
Table 15 ). An active high pulse of longer than 40 ns duration will be required to activate the reset function in
the device.
3.4
Device Identification and Revision
The XR18W750 has the same Device ID as the XR16L275x and XR16V275x. To read the identification code
from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00. Now reading
the content of the DLM will provide 0x0A and reading the content of DLL will provide the revision of the part; for
example, a reading of 0x01 means revision A.
3.5
Internal Registers
The enhanced UART has a set of registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard single 16C550. These
registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO
control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers
(MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible Scratchpad
Register (SPR).
Beyond the general 16C550 features and capabilities, the XR18W750 offers enhanced feature registers
(EMSR, FLVL, EFR, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow control, FIFO trigger
level control, and FIFO level counters. All the register functions are discussed in full detail later in “Section 4.0,
UART INTERNAL REGISTERS” on page 18 .
3.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# and TXRDY# output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the enhanced UART is placed in single-character mode for data transmit or receive
operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by
loading or unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode,
the enhanced UART sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin
when the receive FIFO becomes empty. The following table shows their behavior. Also see Figures 16
through 21 .
T ABLE 3: TXRDY# AND RXRDY# O UTPUTS IN FIFO AND DMA M ODE
P INS
FCR BIT -0=0
(FIFO D ISABLED )
FCR B IT -0=1 (FIFO E NABLED )
FCR Bit-3 = 0
FCR Bit-3 = 1
(DMA Mode Disabled)
(DMA Mode Enabled)
RXRDY#
LOW = 1 byte.
HIGH = no data.
LOW = at least 1 byte in FIFO.
HIGH = FIFO empty.
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs.
LOW to HIGH transition when FIFO empties.
TXRDY#
LOW = THR empty.
LOW = FIFO empty.
LOW = FIFO has at least 1 empty location.
HIGH = byte in THR. HIGH = at least 1 byte in FIFO.
11
HIGH = FIFO is full.
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